Yurdakul, Arda2019-06-282019-06-28200000271-43100271-4310https://hdl.handle.net/20.500.12469/1754https://doi.org/10.1109/ISCAS.2000.858690In this study a synthesis tool using a novel multirate folding technique which handles each FIR filter in a multirate DSP system as a single node is developed. A new architecture is presented for the multiplierless realization of a fold of multirate FIR filters. This synthesizer fully exploits the redundancies (i.e. `idle' and `missing' cycles) and common terms in multirate systems without sacrificing from overall system quality to produce multiplierless multirate systems. It also enables the usage of a single clock for all parts of the circuit.eninfo:eu-repo/semantics/openAccessConference ObjectIV-69IV-724WOS:00008884470001810.1109/ISCAS.2000.8586902-s2.0-0033702736N/AN/A