Rasmi,H.Mosleh,M.Navimipour,N.J.Kheyrandish,M.2024-06-232024-06-23202401536-125Xhttps://doi.org/10.1109/TNANO.2024.3398560https://hdl.handle.net/20.500.12469/5884Today, Complementary Metal-OxideSemiconductor (CMOS) technology faces critical challenges, such as power consumption and current leakage at the nanoscale. Therefore, Atomic Silicon Dangling Bond (ASDB) technology has been proposed as one of the best candidates to replace CMOS technology; due to its high-speed switching and low power consumption. Among the most important issues in ASDB nanotechnology, output stability and robustness against possible faults may be focused. This paper first introduces a novel P-shaped pattern in ASDB, for designing stable and robust primitive logic gates, including AND, NAND, OR, NOR and XOR. Then, two combinational circuits, half-subtractor and full-subtractor, are proposed by the proposed ASDB gates. The simulation results show high output stability as well as adequate robustness, against various defects obtained by the proposed designs; on average, they have improvements of more than 56% and 62%, against DB omission defects and extra cell deposition defects; respectively. Also, the results of the investigations show that the proposed circuits have been improved by 65%, 21% and 2%, in terms of occupied area, energy and occurrence, respectively; compared to the previous works. IEEEeninfo:eu-repo/semantics/closedAccessAtomic Silicon Dangling Bonds (ASDB)Circuit stabilityCircuitsCMOEnginesFullsubtractorHalf-subtractorLayoutLogic gatesNanotechnologyNanotechnologySiliconArticle1910.1109/TNANO.2024.33985602-s2.0-85192983375Q2Q2