Zohaib, MuhammadNavimipour, Nima JafariAydemir, Mehmet TimurAhmadpour, Seyed-Sajad2025-11-152025-11-1520260167-92601872-7522https://doi.org/10.1016/j.vlsi.2025.102572https://hdl.handle.net/20.500.12469/7581Digital signal processing (DSP) is a crucial engineering field dedicated to the processing and analysis of digital signals. DSP is particularly significant in critical sectors such as telecommunications, medical imaging, and secure communications, where it demands high accuracy, reliability, and real-time performance. In addition, the fault-tolerant (F-T) Arithmetic and Logic Unit (ALU) provides a fundamental building block of DSP architectures, enabling the accurate implementation of arithmetic and logical functions that are essential for advanced computational tasks. However, traditional ALUs were designed using complementary metal-oxide semiconductors (CMOS) and very large-scale integration (VLSI), which led to several challenges, such as high energy consumption, high occupied area, and slow operating speed. These limitations can be effectively addressed through nanotechnology, specifically quantum-dot cellular automata (QCA), which offers high speed, reduces occupying area, and has low power consumption. Accordingly, this paper proposes a QCA-based ALU circuit for DSP applications. The proposed designs integrate an F-T full adder (FA), a QCA-based multiplexer (MUX), and an ALU circuit to enhance performance and efficiency for DSP applications. The validation and verification of all suggested designs are performed using the simulation tool QCADesigner.eninfo:eu-repo/semantics/closedAccessDigital Signal ProcessingNanotechnologyArithmetic And Logic UnitQCAFault-TolerantArticle10.1016/j.vlsi.2025.102572