Browsing by Author "Das, Jadav Chandra"

Now showing 1 - 3 of 3

Citation - WoS: 20
Citation - Scopus: 22
An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform
(Elsevier, 2022) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Das, Jadav Chandra; De, Debashis; Yalcin, Senay; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Quantum-dot cellular automata (QCA) is a domain coupling nano-technology that has drawn significant attention for less power consumption, area, and design overhead. It is able to achieve a high speed over the CMOS technology. Recently, the tendency to design reversible circuits has been expanding because of the reduction in energy dissipation. Hence, the QCA is a crucial candidate for reversible circuits in nano-technology. On the other hand, the addition operator is also considered one of the primary operations in digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, full-adders have become popular and extensively solve mathematical problems more efficiently and faster. They are one of the essential fundamental circuits in most digital processing circuits. Therefore, this article first suggests a novel reversible block called the RF-adder block. Then, an effective reversible adder design is proposed using the recommended reversible RF-adder block. The QCAPro and QCADesigner 2.0.3 tools were employed to assess the effectiveness of the suggested reversible full-adder. The outcomes of energy dissipation for the proposed circuit compared to the best previous structure at three different tunneling energy levels indicate a reduction in the power consumption by 45.55%, 38.82%, and 34.62%, respectively. (C) 2022 Elsevier B.V. All rights reserved.
A Nano-Design of Image Masking and Steganography Structure Based on Quantum Technology
(Elsevier, 2025) Salahov, Huseyn; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Das, Jadav Chandra; Rasmi, Hadi; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Secure image storage and transmission require sound encryption methods that resist key exposure while maintaining high image quality. Various encryption approaches have been developed to protect image content and its transmission from unauthorized access. One such method is image masking, where a special mask is generated to conceal information within the original image. Instead of hiding the image visually, the mask creates an intermediate layer that obfuscates the encryption key, eliminating the need to transmit it directly. However, implementing such masking techniques efficiently at the hardware level poses particular challenges. Traditional Complementary Metal-Oxide-Semiconductor (CMOS)-based Very-Large-Scale-Integration (VLSI) systems face scalability issues, excessive heat, and high-power consumption. To overcome these challenges, this study utilizes a nano-scale image masking architecture based on Quantum-dot Cellular Automata (QCA), offering reduced area, lower power dissipation, and faster processing. The core operations utilize a three-input XOR gate, designed as a single-layer QCA structure without rotated cells. While QCA-based approaches improve hardware efficiency, most existing implementations focus only on grayscale images, leaving a gap in colorful image encryption. To address this, the work presents a QCA-based encryption and masking architecture for colored images. The method encrypts an image using a random key to generate a cipher image, which is then XORed with the original image to produce a mask. This process, applied independently to each RGB channel, produces three cipher-mask pairs, embedding steganographic property by concealing key information within the image. The keys are generated using a true random number generator (TRNG) based on cross-coupled loops and crossoriented structures, ensuring high entropy. The design was modeled in QCADesigner 2.0.3, with the encryption/decryption algorithms implemented in Python. Experimental results demonstrated a meaningful reduction in cell count and consumed area compared to the prior designs. Image quality and security analysis confirmed visual fidelity and improved robustness.
Scalable and Low-Power Reversible Logic for Future Devices: QCA and IBM-Based Gate Realization
(Elsevier, 2025) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Zohaib, Muhammad; Misra, Neeraj Kumar; Pour, Mahsa Rastegar; Rasmi, Hadi; Das, Jadav Chandra; 01. Kadir Has University; 05. Faculty of Engineering and Natural Sciences; Computer Engineering
One such revolutionary approach to changing the nano-electronic landscape is integrating reversible logic with quantum dot technology that will replace the conventional complementary metal-oxide semiconductors (CMOS) circuits for ultra-high speed, low density, and energy-efficient digital designs. The implementation of the reversible structure under the most inflexible conditions, as executed by quantum laws, is a highly challenging task. Furthermore, the enormous occupying areas seriously compromise the accuracy of the output in quantum dot circuits. Because of this challenge, quantum circuits can be employed as fundamental building blocks in highperformance digital systems since their implementation has a key impact on overall system performance. This study discusses a paradigm shift in nanoscale digital design by using a 4 x 4 reversible gate that redefines the basis of efficiency and precision. This reversible gate is elaborately used in a reversible full-adder circuit, fully symbolizing the core of minimum area, ultra-low energy consumption, and perfect output accuracy. The proposed reversible circuits have been fully realized using quantum-dot cellular automata technology (QCA), simulated, and verified by the highly reliable tool such as Qiskit IBM and QCADesigner 2.0.3. Furthermore, simulations results demonstrated the superiority of the QCA-based proposed adder, which reduced occupied area by 7.14 %, and cell count by 11.57 %, respectively. This work resolves some problems and opens new boundaries toward the future of digital circuits by addressing the main challenges of stability and pushing the boundaries of reversible logic design.