Browsing by Author "Navimipour, N.J."

Now showing 1 - 4 of 4

Citation Count: 9
The Applications of the Routing Protocol for Low-Power and Lossy Networks (rpl) on the Internet of Mobile Things
(John Wiley and Sons Ltd, 2022) Ghanbari, Z.; Navimipour, N.J.; Hosseinzadeh, M.; Shakeri, H.; Darwesh, A.
Internet of Mobile Things (IoMT) have become very popular recently. The routing protocol for low power and lossy networks (RPL) is standardized for static topologies. However, mobility is the nature of IoT. Mobility serves as a promising candidate to harness hand-off time issues, delay in data transmission, overhead, and low packet delivery rate (PDR) effectively. This study presents a comprehensive account of the mobility-aware RPL-based routing protocols to validate and compare the experimental results. Remarkably, classification methods are used in many articles. The aim is to introduce significant research efforts to improve RPL objective functions (OF) performance in hand-off time, PDR, delay, overhead, and so forth. In this regard, a complete analysis of the existing routing protocols in IoMT has been presented to compare the results. The main focus of this study is on approaches that proposed new OFs for supporting mobility in RPL. Two main categories are considered to study RPL-based routing protocol mechanisms: The mobile and static sink. The related studies on the mobile sink are divided into three groups: Single metric-based OF, composite metric OF, and hybrid routing protocols. Also, the related works based on the static sink are categorized into four groups: Fuzzy logic-based OF, trickle timer-based OF, composite metrics-based OF, and modification control messages-based OF approach. This paper presents a detailed comparison of mechanisms in each category. It also highlights the pros, cons, open issues, and evaluated metrics of each paper. Besides, challenges of mobility in the RPL-based routing protocol mechanism in IoMT for future studies. © 2022 John Wiley & Sons Ltd.
Citation Count: 3
An Efficient Architecture of Adder Using Fault-Tolerant Majority Gate Based on Atomic Silicon Nanotechnology
(Institute of Electrical and Electronics Engineers Inc., 2023) Ahmadpour, S.; Navimipour, N.J.; Bahar, A.N.; Yalcin, S.
It is expected that Complementary Metal Oxide Semiconductor (CMOS) implementation with ever-smaller transistors will soon face significant issues such as device density, power consumption, and performance due to the requirement for challenging fabrication processes. Therefore, a new and promising computation paradigm, nanotechnology, can replace CMOS technology. In addition, a new frontier in computing is opened up by nanotechnology called atomic silicon, which has the same extraordinary behavior as quantum dots. Furthermore, Dangling Bond (DB) quantum dots play a vital role in atomic silicon nanotechnology. On the other hand, atomic silicon circuits are highly prone to defects, so suggested fault-tolerant structures in this technology play important roles. The addition operator holds immense significance in digital signal processing and computer arithmetic operations, making it one of the primary operations in digital circuits. Consequently, full adders have gained popularity and find widespread use in efficiently solving mathematical problems. In the following paper, we will explore the development of an efficient fault-tolerant 3-input majority gate (FT-MV3) using DBs, further enhancing the capabilities of digital circuits. A rule-based approach to the redundant DB achieves a less complex and more robust atomic silicon layout for the MV3. We use the powerful SiQAD tool to simulate all the proposed circuits. In addition, to confirm the efficiency of the proposed gate, all common defects, such as single and double dangling bond omission defects and DB dislocation defects, are examined. The suggested majority gate is 100% and 66.66% tolerant against single and double DB omission defects, respectively. Furthermore, a new full adder design is introduced using the suggested FT-MV3 gate. The results show that the suggested full adder is 44.44% and 35.35% tolerant against single and double DB omission defects. Finally, a fault-tolerant four-bit adder is designed based on the proposed full adder. IEEE
Citation Count: 7
An Energy-Aware Scheme for Solving the Routing Problem in the Internet of Things Based on Jaya and Flower Pollination Algorithms
(Springer Science and Business Media Deutschland GmbH, 2023) Sadrishojaei, M.; Navimipour, N.J.; Reshadi, M.; Hosseinzadeh, M.
Clustering and routing protocols for Internet of Things (IoT) need to consider energy usage and how to reduce it. Unbalanced power usage is a common concern with current solutions to cluster-based routing problems in the IoT ecosystem. This research developed a swarm intelligence-based clustering technique to achieve a more uniform dispersion of cluster heads. The data packets across cluster heads and the sink are routed via a Jaya algorithm. Based on average remaining energy, number of active nodes, number of nodes that have failed or have been removed from the network, and overall network throughput, this combined clustering and routing method's quality has been assessed. The integrative clustering and routing protocol based on the flower pollination algorithm and Jaya algorithm described here exhibit considerable improvements over the current state-of-the-art. The network throughput and the number of the alive node are essential statistics for evaluating IoT in which battery-powered devices periodically acquire surroundings data and transmit gathered samples to a base station. The proposed strategy improved network throughput and the number of dead nodes by at least 14% and 18%, respectively. © 2023, The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature.
Citation Count: 0
Towards a Scalable and Efficient Full- Adder Structure in Atomic Silicon Dangling Band Technology
(Elsevier B.V., 2025) Rasmi, H.; Mosleh, M.; Navimipour, N.J.; Kheyrandish, M.
Atomic Silicon Dangling Bond (ASDB) is a promising new nanoscale technology for fabricating logic gates and digital circuits. This technology offers tremendous advantages, such as small size, high speed, and low power consumption. As science and technology progress, ASDB technology may eventually replace the current VLSI technology. This nanoscale technology is still in its early stages of development. Recently, many computing circuits, such as full-adder, have been designed. However, these circuits have a common fundamental problem; they consume a lot of energy and occupy a lot of area, which reduces the performance of complex circuits. This paper proposes a novel ASDB layout for designing an efficient full-adder circuit in ASDB technology. Moreover, a four-bit ASDB ripple carry adder(RCA) is designed using the proposed ASDB full-adder. The proposed ASDB full-adder not only improves the stability of the output but also surpasses the previous works, in terms of energy and accuracy,by 90% and 38%, respectively. Also, it has very favorable conditions in terms of occupied area and is resistant to DB misalignment defects. © 2024