Browsing by Author "Ul Ain, Noor"

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Citation - WoS: 6
Citation - Scopus: 8
Design and Implementation of a Nano-Scale High-Speed Multiplier for Signal Processing Applications
(Elsevier, 2024) Ahmadpour, Seyed-Sajad; Kerestecioğlu, Feza; Jafari Navimipour, Nima; Ul Ain, Noor; Kerestecioglu, Feza; Yalcin, Senay; Avval, Danial Bakhshayeshi; Hosseinzadeh, Mehdi
Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technologybased multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.
Citation - WoS: 12
Citation - Scopus: 12
A Nano-Scale Design of a Multiply-Accumulate Unit for Digital Signal Processing Based on Quantum Computing
(Springer, 2024) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari; Yalcin, Senay; Bakhshayeshi Avval, Danial; Ul Ain, Noor
Digital signal processing (DSP) is used in computer processing to conduct different signal-processing tasks. The DSPs are used in the series numbers representing a continuous variable in a domain such as time, area, or frequency. The multiply-accumulate (MAC) unit is crucial in various DSP applications, including convolution, discrete cosine transform (DCT), Fourier Transform, etc. Thus, all DSPs contain a critical MAC unit in signal processing. The MAC unit conducts multiplication and accumulation operations for continuous and complicated DSP application processes. On the other hand, in the MAC structure, the stability of the circuit and the occupied area pose some significant challenges. However, high-performance quantum technology can easily overcome all the previous shortcomings. Hence, this paper suggests an efficient MAC for DSP applications using a Vedic multiplier, half adder, and accumulator based on quantum technology. All the proposed structures have used a single-layer layout without rotated cells. The suggested architecture is designed and validated based on the QCADesigner 2.0.3 tool. The findings revealed that all the developed circuits have a simple architecture with fewer quantum cells, optimal area, and low latency.
Citation - WoS: 0
Retraction: a Nano-Scale Design of a Multiply-Accumulate Unit for Digital Signal Processing Based on Quantum Computing
(Springer, 2024) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Navimipour, Nima Jafari; Yalcin, Senay; Avval, Danial Bakhshayeshi; Ul Ain, Noor
[No Abstract Available]
Citation - WoS: 1
Citation - Scopus: 1
Secure Quantum-Based Adder Design for Protecting Machine Learning Systems Against Side-Channel Attacks
(Elsevier, 2025) Jafari Navimipour, Nima; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Diakina, E.; Kassa, Sankit R.
Machine learning (ML) has recently been adopted in various application domains. Usually, a well-performing ML model relies on a large volume of training data and powerful computational resources. Recently, hardware accelerators utilizing field programmable gate arrays (FPGAs) have been developed to provide high-performance hardware while maintaining the required accuracy for ML tools. However, one of the main challenges hindering the FPGA-based ML models is their susceptibility to adversarial attacks, such as physical side-channel attacks. In this study, various kinds of countermeasures, including masking and hiding techniques, are examined to mitigate the aforementioned shortcomings and enhance the security of FPGA-based ML systems. In addition to FPGA-based defenses, the advantages of quantum computing for designing circuits to enhance data protection are also elaborated. However, concerning FPGA-based ML models, which are used to defend against physical side-channel attacks, quantum dot cellular automata (QCA) offers a more promising option. Its inherent security, lower power consumption, higher speed, and reduced vulnerability to side-channel leakage make it the best alternative. Therefore, this study emphasizes the implementation of the quantum nature of QCA to protect valuable information against physical side-channel attacks. It also offers quantum masking circuits for protecting sensitive information in machine learning systems, including XOR, adder, and RCA. Furthermore, the presented work advocates for leveraging QCA technology to augment the security of machine learning systems by mitigating the disclosure of sensitive data. The proposed QCA-based masked designs, which include an adder and a ripple carry adder (RCA), pose some qualities, which include a single-layer structure, minimal cell count, and low latency. When compared with the best counterparts among the recommended designs, these designs exhibit significant improvements regarding cell consumption and occupied area, with improvements of 33.3% and 36.6% respectively.