A synthesis tool for the multiplierless realization of FIR-based multirate DSP systems

dc.contributor.authorYurdakul, Arda
dc.date.accessioned2019-06-28T11:12:00Z
dc.date.available2019-06-28T11:12:00Z
dc.date.issued2000
dc.departmentFakülteler, Mühendislik ve Doğa Bilimleri Fakültesi, Bilgisayar Mühendisliği Bölümüen_US
dc.description.abstractIn this study a synthesis tool using a novel multirate folding technique which handles each FIR filter in a multirate DSP system as a single node is developed. A new architecture is presented for the multiplierless realization of a fold of multirate FIR filters. This synthesizer fully exploits the redundancies (i.e. `idle' and `missing' cycles) and common terms in multirate systems without sacrificing from overall system quality to produce multiplierless multirate systems. It also enables the usage of a single clock for all parts of the circuit.en_US]
dc.identifier.citation0
dc.identifier.doi10.1109/ISCAS.2000.858690en_US
dc.identifier.endpageIV-72
dc.identifier.issn0271-4310en_US
dc.identifier.issn0271-4310
dc.identifier.scopus2-s2.0-0033702736en_US
dc.identifier.scopusqualityN/A
dc.identifier.startpageIV-69en_US
dc.identifier.urihttps://hdl.handle.net/20.500.12469/1754
dc.identifier.urihttps://doi.org/10.1109/ISCAS.2000.858690
dc.identifier.volume4en_US
dc.identifier.wosWOS:000088844700018en_US
dc.identifier.wosqualityN/A
dc.institutionauthorYurdakul, Ardaen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.journal2000 IEEE International Symposium on Circuits and Systems (ISCAS)en_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.titleA synthesis tool for the multiplierless realization of FIR-based multirate DSP systemsen_US
dc.typeConference Objecten_US
dspace.entity.typePublication

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