A Synthesis Tool for the Multiplierless Realization of Fir-Based Multirate Dsp Systems

dc.contributor.author Yurdakul, Arda
dc.date.accessioned 2019-06-28T11:12:00Z
dc.date.available 2019-06-28T11:12:00Z
dc.date.issued 2000
dc.department Fakülteler, Mühendislik ve Doğa Bilimleri Fakültesi, Bilgisayar Mühendisliği Bölümü en_US
dc.description.abstract In this study a synthesis tool using a novel multirate folding technique which handles each FIR filter in a multirate DSP system as a single node is developed. A new architecture is presented for the multiplierless realization of a fold of multirate FIR filters. This synthesizer fully exploits the redundancies (i.e. `idle' and `missing' cycles) and common terms in multirate systems without sacrificing from overall system quality to produce multiplierless multirate systems. It also enables the usage of a single clock for all parts of the circuit. en_US]
dc.identifier.citationcount 0
dc.identifier.doi 10.1109/ISCAS.2000.858690 en_US
dc.identifier.endpage IV-72
dc.identifier.issn 0271-4310 en_US
dc.identifier.issn 0271-4310
dc.identifier.scopus 2-s2.0-0033702736 en_US
dc.identifier.startpage IV-69 en_US
dc.identifier.uri https://hdl.handle.net/20.500.12469/1754
dc.identifier.uri https://doi.org/10.1109/ISCAS.2000.858690
dc.identifier.volume 4 en_US
dc.identifier.wos WOS:000088844700018 en_US
dc.institutionauthor Yurdakul, Arda en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.relation.journal 2000 IEEE International Symposium on Circuits and Systems (ISCAS) en_US
dc.relation.publicationcategory Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı en_US
dc.rights info:eu-repo/semantics/openAccess en_US
dc.scopus.citedbyCount 1
dc.title A Synthesis Tool for the Multiplierless Realization of Fir-Based Multirate Dsp Systems en_US
dc.type Conference Object en_US
dc.wos.citedbyCount 0
dspace.entity.type Publication

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