Toward implementing robust quantum logic circuits using effectual fault-tolerant majority voter gate

dc.authorscopusid58850310800
dc.authorscopusid55411379000
dc.authorscopusid57202686649
dc.authorscopusid55897274300
dc.authorscopusid53983497500
dc.contributor.authorJafari Navimipour, Nima
dc.contributor.authorMosleh, Mohammad
dc.contributor.authorAhmadpour, Seyed-Sajad
dc.contributor.authorNavimipour, Nima Jafari
dc.contributor.authorShahrbanoonezhad, Alireza
dc.date.accessioned2024-06-23T21:36:59Z
dc.date.available2024-06-23T21:36:59Z
dc.date.issued2024
dc.departmentKadir Has Universityen_US
dc.department-temp[Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari] Islamic Azad Univ, Dept Comp Engn, Dehloran Branch, Dehloran, Iran; [Mosleh, Mohammad] Islamic Azad Univ, Dept Comp Engn, Dezful Branch, Dezful, Iran; [Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari] Kadir Has Univ, Dept Comp Engn, Istanbul, Turkiye; [Navimipour, Nima Jafari] Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu 64002, Taiwanen_US
dc.description.abstractQuantum -dot Cellular Automata (QCA) has emerged as a revolutionary technology for nano-scale computing circuits and a promising alternative to conventional transistor-based technologies. However, the susceptibility to defects during circuit synthesis is a pivotal challenge, undermining its potential. This study seeks to introduce an innovative and robust fault-tolerant 3 -input majority voter gate comprising 16 simple cells. The primary objective is to enhance the gate's resilience against two specific defects: one-cell omission and extra-cell deposition. Preliminary assessments indicate that the introduced gate achieves remarkable tolerance rates of 100% for one-cell omission and 89.47% for extra-cell deposition defects. A comprehensive evaluation is used based on the QCADesigner 2.0.3 simulator to validate the gate's performance, supplemented by physical proofs. Furthermore, leveraging the novel gate structure, this paper extends its application to the design of fault-tolerant flip-flops and multiplexer circuits. These building blocks are then employed to construct three distinct fault-tolerant sequential circuits.en_US
dc.identifier.citation1
dc.identifier.doi10.1016/j.mseb.2023.117161
dc.identifier.issn0921-5107
dc.identifier.issn1873-4944
dc.identifier.scopus2-s2.0-85183457532
dc.identifier.scopusqualityQ2
dc.identifier.urihttps://doi.org/10.1016/j.mseb.2023.117161
dc.identifier.urihttps://hdl.handle.net/20.500.12469/5680
dc.identifier.volume301en_US
dc.identifier.wosWOS:001170917300001
dc.identifier.wosqualityQ2
dc.language.isoenen_US
dc.publisherElsevieren_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectNanometer-fault-tolerant memoryen_US
dc.subjectCounteren_US
dc.subjectRAM cellen_US
dc.subjectShift registeren_US
dc.titleToward implementing robust quantum logic circuits using effectual fault-tolerant majority voter gateen_US
dc.typeArticleen_US
dspace.entity.typePublication
relation.isAuthorOfPublication0fb3c7a0-c005-4e5f-a9ae-bb163df2df8e
relation.isAuthorOfPublication.latestForDiscovery0fb3c7a0-c005-4e5f-a9ae-bb163df2df8e

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