Toward implementing robust quantum logic circuits using effectual fault-tolerant majority voter gate
dc.authorscopusid | 58850310800 | |
dc.authorscopusid | 55411379000 | |
dc.authorscopusid | 57202686649 | |
dc.authorscopusid | 55897274300 | |
dc.authorscopusid | 53983497500 | |
dc.contributor.author | Jafari Navimipour, Nima | |
dc.contributor.author | Mosleh, Mohammad | |
dc.contributor.author | Ahmadpour, Seyed-Sajad | |
dc.contributor.author | Navimipour, Nima Jafari | |
dc.contributor.author | Shahrbanoonezhad, Alireza | |
dc.date.accessioned | 2024-06-23T21:36:59Z | |
dc.date.available | 2024-06-23T21:36:59Z | |
dc.date.issued | 2024 | |
dc.department | Kadir Has University | en_US |
dc.department-temp | [Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari] Islamic Azad Univ, Dept Comp Engn, Dehloran Branch, Dehloran, Iran; [Mosleh, Mohammad] Islamic Azad Univ, Dept Comp Engn, Dezful Branch, Dezful, Iran; [Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari] Kadir Has Univ, Dept Comp Engn, Istanbul, Turkiye; [Navimipour, Nima Jafari] Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu 64002, Taiwan | en_US |
dc.description.abstract | Quantum -dot Cellular Automata (QCA) has emerged as a revolutionary technology for nano-scale computing circuits and a promising alternative to conventional transistor-based technologies. However, the susceptibility to defects during circuit synthesis is a pivotal challenge, undermining its potential. This study seeks to introduce an innovative and robust fault-tolerant 3 -input majority voter gate comprising 16 simple cells. The primary objective is to enhance the gate's resilience against two specific defects: one-cell omission and extra-cell deposition. Preliminary assessments indicate that the introduced gate achieves remarkable tolerance rates of 100% for one-cell omission and 89.47% for extra-cell deposition defects. A comprehensive evaluation is used based on the QCADesigner 2.0.3 simulator to validate the gate's performance, supplemented by physical proofs. Furthermore, leveraging the novel gate structure, this paper extends its application to the design of fault-tolerant flip-flops and multiplexer circuits. These building blocks are then employed to construct three distinct fault-tolerant sequential circuits. | en_US |
dc.identifier.citation | 1 | |
dc.identifier.doi | 10.1016/j.mseb.2023.117161 | |
dc.identifier.issn | 0921-5107 | |
dc.identifier.issn | 1873-4944 | |
dc.identifier.scopus | 2-s2.0-85183457532 | |
dc.identifier.scopusquality | Q2 | |
dc.identifier.uri | https://doi.org/10.1016/j.mseb.2023.117161 | |
dc.identifier.uri | https://hdl.handle.net/20.500.12469/5680 | |
dc.identifier.volume | 301 | en_US |
dc.identifier.wos | WOS:001170917300001 | |
dc.identifier.wosquality | Q2 | |
dc.language.iso | en | en_US |
dc.publisher | Elsevier | en_US |
dc.relation.publicationcategory | Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı | en_US |
dc.rights | info:eu-repo/semantics/closedAccess | en_US |
dc.subject | Nanometer-fault-tolerant memory | en_US |
dc.subject | Counter | en_US |
dc.subject | RAM cell | en_US |
dc.subject | Shift register | en_US |
dc.title | Toward implementing robust quantum logic circuits using effectual fault-tolerant majority voter gate | en_US |
dc.type | Article | en_US |
dspace.entity.type | Publication | |
relation.isAuthorOfPublication | 0fb3c7a0-c005-4e5f-a9ae-bb163df2df8e | |
relation.isAuthorOfPublication.latestForDiscovery | 0fb3c7a0-c005-4e5f-a9ae-bb163df2df8e |