Processor Design and Application of Futuristic

dc.authorscopusid56405207500
dc.authorscopusid57222637349
dc.authorscopusid55823161800
dc.authorscopusid57202686649
dc.authorscopusid56912219900
dc.authorscopusid59125628000
dc.authorwosidBhoi, Bandan/N-2374-2017
dc.authorwosidKassa, Sankit/G-5769-2015
dc.authorwosidMisra, Neeraj/B-9442-2015
dc.authorwosidJafari Navimipour, Nima/Aaf-5662-2021
dc.contributor.authorMisra, Neeraj Kumar
dc.contributor.authorPathak, Nirupma
dc.contributor.authorBhoi, Bandan Kumar
dc.contributor.authorAhmadpour, Seyed-Sajad
dc.contributor.authorKassa, Sankit R.
dc.contributor.authorNavimipour, Nima Jafari
dc.date.accessioned2025-05-15T18:39:21Z
dc.date.available2025-05-15T18:39:21Z
dc.date.issued2025
dc.departmentKadir Has Universityen_US
dc.department-temp[Misra, Neeraj Kumar] VIT AP Univ, Sch Elect Engn, Amaravati 522237, Andhra Pradesh, India; [Pathak, Nirupma] Koneru Lakshmaiah Educ Fdn, Dept Comp Sci & Engn, Vaddeswaram 522502, Andhra Pradesh, India; [Bhoi, Bandan Kumar] Veer Surendra Sai Univ Technol, Dept Elect & Telecommun, Burla 768018, Odisha, India; [Ahmadpour, Seyed-Sajad] Kadir Has Univ, Fac Engn & Nat Sci, Dept Comp Engn, Istanbul, Turkiye; [Kassa, Sankit R.] Symbiosis Int Univ Pune, Symbiosis Inst Technol, Elect & Telecommun Dept, Pune, Maharashtra, India; [Navimipour, Nima Jafari] Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu 64002, Taiwanen_US
dc.description.abstractMany devices consist of low-power processor. Quantum-dot-cellular-automata (QCA) based processor designs provide enhanced performance compared with conventional metal-oxide-semiconductor (MOS) based processors. Nanocomputing-based processors are often energy-efficient. We have developed Nanotechnology QCA-based different subcomponents of processor such as 2-to-4 decoder, 3-to-8 decoder, Delay Flip-flop (D-FF), and sequence counter. A potential energy proof has been measured in the 2-to-4 decoder design. The synthesis approach algorithm has been presented for all designs. Further, the potential energy calculation results show for 2-to-4 decoder. According to the synthesis results 2-to-4 decoder has improved 82.3% cell count, 86% area, and 85% latency over previous work. Comparing the primitive results with the prior one, results improved by 64% and 76% in terms of cell count and area in the design of the 3-to-8 decoder. Among the different components of the processor is D-FF, which has an improvement of 66.37% in cell counts and 62.5% in area over the prior design. Primitive results have improved, including latency, cell count, and area, showing the proposed processor design is comparable to lowpower devices and high speed. In terms of balance power, the proposed subcomponent of the processor will benefit low power device.en_US
dc.description.woscitationindexEmerging Sources Citation Index
dc.identifier.doi10.2298/FUEE2501163M
dc.identifier.endpage186en_US
dc.identifier.issn0353-3670
dc.identifier.issn2217-5997
dc.identifier.issue1en_US
dc.identifier.scopus2-s2.0-105002062322
dc.identifier.scopusqualityN/A
dc.identifier.startpage163en_US
dc.identifier.urihttps://doi.org/10.2298/FUEE2501163M
dc.identifier.urihttps://hdl.handle.net/20.500.12469/7314
dc.identifier.volume38en_US
dc.identifier.wosWOS:001460636600011
dc.identifier.wosqualityN/A
dc.language.isoenen_US
dc.publisherUniv Nisen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectQcaen_US
dc.subjectComputingen_US
dc.subjectProcessoren_US
dc.subjectSequence Counteren_US
dc.subjectDecoderen_US
dc.subjectNanotechnologyen_US
dc.subjectAlgorithmen_US
dc.subjectLow Poweren_US
dc.titleProcessor Design and Application of Futuristicen_US
dc.typeArticleen_US
dspace.entity.typePublication

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