Browsing by Author "Kerestecioglu,F."

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Citation Count: 0
Design and implementation of a nano-scale high-speed multiplier for signal processing applications
(Elsevier B.V., 2024) Kerestecioğlu, Feza; Navimipour,N.J.; Ain,N.U.; Kerestecioglu,F.; Yalcin,S.; Avval,D.B.; Hosseinzadeh,M.
Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area. © 2024 Elsevier B.V.
Citation Count: 1
A New Nano-Design of an Efficient Synchronous Full-Adder/Subtractor Based on Quantum-Dots
(ISRES Publishing, 2023) Kerestecioğlu, Feza; Navimipour,N.J.; Kerestecioglu,F.
Quantum-dot cellular automata (QCA), known as one of the alternative technologies of CMOS technology, promises to design digital circuits with extra low-power, extremely dense, and high-speed structures. Moreover, the next generation of digital systems will be used QCA as desired technology. In designing arithmetic circuits, efficient designs such as full-adder and full-subtractor can play a significant role. In addition, they are considering the most used structures in digital operations. Furthermore, full-adder and fullsubtractor are always effective parts of all complex and well-known circuits such as Arithmetic Logic Unit (ALU), Microprocessors, etc. This paper proposes low complexity and high-speed QCA coplanar synchronous full-adder/subtractor structures by applying formulations based on the Exclusive-OR gate to decrease energy consumption. The proposed design is simulated using QCADesigner 2.0.3. The simulation results confirm the efficiency of the proposed circuit. Moreover, comparative investigation indicates the superiority of proposed designs compared to state-of-the-art designs. Finally, the suggested QCA coplanar synchronous fulladder/subtractor shows 5.88% and 7.69% improvement in consumed cells relative to the best full adder and full subtractor, respectively. © 2023 Published by ISRES.