Browsing by Author "Rasmi, Hadi"

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A Low-Latency and Area-Efficient QCA-Based Quantum-Dot Design for Next-Generation Digital Sustainable Systems
(Elsevier, 2025) Zohaib, Muhammad; Ahmadpour, Seyed-Sajad; Rasmi, Hadi; Khan, Angshuman; Navimipour, Nima Jafari; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Digital sustainable system plays a vital role in the advancement of dynamic industries, including agriculture, healthcare, smart cities, Edge Artificial Intelligence (AI), and the Internet of Things (IoT), by facilitating highspeed, low-power, and highly compressed processing. These systems are based on the capabilities of real-time execution, processing, and analysis of large-scale information with extreme power and area limitations. However, traditional Arithmetic Logic Units (ALUs) based on complementary metal-oxide semiconductors (CMOS) are becoming challenging in terms of scalability, power consumption, space demand, and nanoscale fabrication. The ALU is one of the most important parts of such systems and has a direct effect on the overall computing performance, but current implementations cannot sustain the requirements of next-generation applications. To overcome these shortcomings, this paper offers an area-efficient and low-latency ALU that can be designed with the quantum-dot cellular automata (QCA) technology, with the advantage of employing area-efficient layout and simple cell design. The proposed QCA-based ALU has high performance, less delay, and less energy consumption, which makes it properly suitable for the next generation of digital sustainable systems applications. The outcome of the simulation indicates that there are considerable performance gains, such as an 82.37% decrease in energy consumption, and a 9.21% decrease in area relative to current available design. These enhancements emphasize the power of QCA technology as a scalable and low-energy consumption alternative to CMOS in the realization of critical computing components in sustainable digital systems.
A Nano-Design of Image Masking and Steganography Structure Based on Quantum Technology
(Elsevier, 2025) Salahov, Huseyn; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Das, Jadav Chandra; Rasmi, Hadi; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Secure image storage and transmission require sound encryption methods that resist key exposure while maintaining high image quality. Various encryption approaches have been developed to protect image content and its transmission from unauthorized access. One such method is image masking, where a special mask is generated to conceal information within the original image. Instead of hiding the image visually, the mask creates an intermediate layer that obfuscates the encryption key, eliminating the need to transmit it directly. However, implementing such masking techniques efficiently at the hardware level poses particular challenges. Traditional Complementary Metal-Oxide-Semiconductor (CMOS)-based Very-Large-Scale-Integration (VLSI) systems face scalability issues, excessive heat, and high-power consumption. To overcome these challenges, this study utilizes a nano-scale image masking architecture based on Quantum-dot Cellular Automata (QCA), offering reduced area, lower power dissipation, and faster processing. The core operations utilize a three-input XOR gate, designed as a single-layer QCA structure without rotated cells. While QCA-based approaches improve hardware efficiency, most existing implementations focus only on grayscale images, leaving a gap in colorful image encryption. To address this, the work presents a QCA-based encryption and masking architecture for colored images. The method encrypts an image using a random key to generate a cipher image, which is then XORed with the original image to produce a mask. This process, applied independently to each RGB channel, produces three cipher-mask pairs, embedding steganographic property by concealing key information within the image. The keys are generated using a true random number generator (TRNG) based on cross-coupled loops and crossoriented structures, ensuring high entropy. The design was modeled in QCADesigner 2.0.3, with the encryption/decryption algorithms implemented in Python. Experimental results demonstrated a meaningful reduction in cell count and consumed area compared to the prior designs. Image quality and security analysis confirmed visual fidelity and improved robustness.
Citation - WoS: 6
Citation - Scopus: 8
A New Median Filter Circuit Design Based on Atomic Silicon Quantum-Dot for Digital Image Processing and IoT Applications
(IEEE-Inst Electrical Electronics Engineers Inc, 2025) Ahmadpour, Seyed-Sajad; Avval, Danial Bakhshayeshi; Navimipour, Nima Jafari; Rasmi, Hadi; Heidari, Arash; Kassa, Sankit; Patidar, Mukesh; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Digital image processing (DIP) is the ability to manipulate digital photographs via algorithms for pattern detection, segmentation, enhancement, and noise reduction. In addition, the Internet of Things (IoT) acts as the eye and system for all DIP in various applications. It can possess a camera or another image sensor in order to capture real-time data from its environment. All vital data is processed by image processing in such a way that it recognizes the object, detects an anomaly, and automatically decides in real-time. In addition, in an IoT system, the median filter is the technique used for noise reduction by substituting the value of the pixel with the central value of the surrounding pixels. It provides speed and efficiency for quick analysis in all IoT systems. However, the images can get corrupted, especially in resource-constrained IoT devices with small cameras, because of random glitches. Moreover, using new quantum technology like atomic-scale silicon dangling bond (DB) logic circuits, which have advanced in fabrication and become a strong contender for field-coupled nano-computing, can solve previous problems in IoT systems. In this article, we propose a unique quantum CSM based on two new proposed Mux and De-mux. The proposed CSM can be used for computational circuits like median filter circuits (MFC) in a wide range of digital circuits, specifically IoT devices. The proposed design is verified and validated using the powerful SiQAD tool. When comparing CSM to the newest designs, the suggested quantum circuit uses 85% less energy and takes up 61% less area.
Citation - WoS: 8
Citation - Scopus: 8
Novel efficient and scalable design of full-adder in atomic silicon dangling bonds (ASDB) technology
(Iop Publishing Ltd, 2023) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Atomic Silicon Dangling Bonds (ASDB) is an advanced emerging nanotechnology to replace CMOS technology; because it allows the designing of circuits with very high-speed and low-density. However, one of the most critical challenges in implementing circuits in ASDB nanotechnology is output stability and possible defects, such as DB omission, DB misalignment, and DB extra deposition, which can be overcome using a suitable designing pattern. Therefore, developing stable and robust structures is considered as one of essential topics in ASDB. This paper first proposes two novel and stable computing circuits, including a three-input majority voter (MV3) and three-input XOR (XOR3); based on triangular and rhombus patterns, respectively. Then, an efficient ASDB full-adder is designed using the suggested MV3 and XOR3 gates. Finally, two and four-bit ripple carry adders are developed using proposed full-adder. Simulation results indicate that the suggested MV3 and XOR3 are superior to previous designs, by more than 80%, 48%, and 9.5%, averagely; in terms of occupied area, energy, and occurrence, respectively. Moreover, the proposed gates are investigated against possible defects, and the results show high stability.
Citation - WoS: 1
Citation - Scopus: 1
Proposing and Developing Low-Power Quantum Arithmetic Logic Units (QALUs) for Smart Grids and the Internet of Energy
(IEEE, 2025) Ahmadpour, Seyed Sajad; Zohaib, Muhammad; Rasmi, Hadi; Navimipour, Nima Jafari; Alsaleh, Omar I.; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
The advancement of modern power systems has produced smart grids by implementing intelligent control systems linked with digital communication technology to boost reliability and sustainability while improving operational efficiency. The Internet of Energy (IoE) represents an advanced version of smart grids that adopt real-time monitoring with decentralized energy management and dynamic power distribution to maximize energy efficiency. The development of the IoE encounters major obstacles because it handles problems involving power consumption, alongside calculation speed, network stability, the protection of information resources, and problems related to system performance management. The solution to these difficulties demands innovative technological methods for implementation. The authors present Quantum Arithmetic Logic Units (QALUs), which serve as a groundbreaking technology for optimizing performance and energy usage in smart grids, together with IoE systems. The combination of nanotechnology elements with quantum computing rules enables QALUs to operate with minimal power requirements alongside simultaneous processing features and error-resilient operations, which suits them for immediate energy supervision purposes. The QALU design proposal demonstrates the evaluation of power efficiency performance while showing operational accuracy levels and scalability capabilities for a future energy network revolution. The proposed ALU brings improvements in all areas, including power consumption, with a 99.29results. This paper marks a transformative advancement in the development of quantum-enhanced smart grids, which pave the way for enhanced, sustainable, and secure optimized energy systems.
Scalable and Low-Power Reversible Logic for Future Devices: QCA and IBM-Based Gate Realization
(Elsevier, 2025) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Zohaib, Muhammad; Misra, Neeraj Kumar; Pour, Mahsa Rastegar; Rasmi, Hadi; Das, Jadav Chandra; 01. Kadir Has University; 05. Faculty of Engineering and Natural Sciences; Computer Engineering
One such revolutionary approach to changing the nano-electronic landscape is integrating reversible logic with quantum dot technology that will replace the conventional complementary metal-oxide semiconductors (CMOS) circuits for ultra-high speed, low density, and energy-efficient digital designs. The implementation of the reversible structure under the most inflexible conditions, as executed by quantum laws, is a highly challenging task. Furthermore, the enormous occupying areas seriously compromise the accuracy of the output in quantum dot circuits. Because of this challenge, quantum circuits can be employed as fundamental building blocks in highperformance digital systems since their implementation has a key impact on overall system performance. This study discusses a paradigm shift in nanoscale digital design by using a 4 x 4 reversible gate that redefines the basis of efficiency and precision. This reversible gate is elaborately used in a reversible full-adder circuit, fully symbolizing the core of minimum area, ultra-low energy consumption, and perfect output accuracy. The proposed reversible circuits have been fully realized using quantum-dot cellular automata technology (QCA), simulated, and verified by the highly reliable tool such as Qiskit IBM and QCADesigner 2.0.3. Furthermore, simulations results demonstrated the superiority of the QCA-based proposed adder, which reduced occupied area by 7.14 %, and cell count by 11.57 %, respectively. This work resolves some problems and opens new boundaries toward the future of digital circuits by addressing the main challenges of stability and pushing the boundaries of reversible logic design.
Citation - Scopus: 2
Sustainable IoT Solutions: Developing a Quantum-Aware Circuit for Improving Energy Efficiency Based on Atomic Silicon
(Elsevier, 2025) Rasmi, Hadi; Ahmadpour, Seyed Sajad; Seyyedabbasi, Amir; Navimipour, Nima Jafari; Khan, Wasiq; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Internet of Things (IoT) can be described as a network of physical objects equipped with sensors, processing power, software, and any other types of technology that allows them to communicate and share data with other devices and systems. The proliferation of IoT is conditional on developing energy-saving blocks of computation with sustained connectivity and real-time information processing capabilities. Traditional technologies like CMOS and VLSI circuits face critical failures at scales below 4 nm, including excessive current leakages, high energy consumption, and thermal instability, which make them less appropriate for future micro-scale IoT chips. To overcome such limitations, a new alternative technology called Atomic Silicon Dangling Bond (ASDB) nanotechnology has been developed, leveraging atomistic accuracy in countering CMOS-related inefficiencies and supporting quantum-inspired computational processes. Since Arithmetic and Logic Unit (ALU) is a primary unit of any digital system like IoT, this work introduces the necessity of quantum-aware ALU development, taking a quantum-inspired computational mechanism and leveraging ASDB's native quantum behavior for increased performance, accuracy, and efficiency in IoT systems. A single-bit ALU for micro-IoT blocks is developed using ASDB nanotechnology with robust computational design to guarantee operational integrity. The design is analyzed through SiQAD simulator in terms of energy consumption, logical accuracy, and area consumption. The proposed ALU in this work demonstrates a reduction in occupied area and quantum cell count, highlighting a significant step toward ultra-dense integration. Furthermore, with an energy consumption reduction of 3.19% compared to the best design, this ALU offers a sustainable and practical solution for lowpower IoT applications in the future.
Citation - Scopus: 2
Towards a Scalable and Efficient Full- Adder Structure in Atomic Silicon Dangling Band Technology
(Elsevier, 2025) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Atomic Silicon Dangling Bond (ASDB) is a promising new nanoscale technology for fabricating logic gates and digital circuits. This technology offers tremendous advantages, such as small size, high speed, and low power consumption. As science and technology progress, ASDB technology may eventually replace the current VLSI technology. This nanoscale technology is still in its early stages of development. Recently, many computing circuits, such as full-adder, have been designed. However, these circuits have a common fundamental problem; they consume a lot of energy and occupy a lot of area, which reduces the performance of complex circuits. This paper proposes a novel ASDB layout for designing an efficient full-adder circuit in ASDB technology. Moreover, a four-bit ASDB ripple carry adder(RCA) is designed using the proposed ASDB full-adder. The proposed ASDB fulladder not only improves the stability of the output but also surpasses the previous works, in terms of energy and accuracy,by 90% and 38%, respectively. Also, it has very favorable conditions in terms of occupied area and is resistant to DB misalignment defects.
Citation - WoS: 7
Citation - Scopus: 8
Towards Atomic Scale Quantum Dots in Silicon: an Ultra-Efficient and Robust Subtractor Using Proposed P-Shaped Pattern
(Ieee-inst Electrical Electronics Engineers inc, 2024) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
Today, Complementary Metal-Oxide-Semiconductor (CMOS) technology faces critical challenges, such as power consumption and current leakage at the nanoscale. Therefore, Atomic Silicon Dangling Bond (ASDB) technology has been proposed as one of the best candidates to replace CMOS technology; due to its high-speed switching and low power consumption. Among the most important issues in ASDB nanotechnology, output stability and robustness against possible faults may be focused. This paper first introduces a novel P-shaped pattern in ASDB, for designing stable and robust primitive logic gates, including AND, NAND, OR, NOR and XOR. Then, two combinational circuits, half-subtractor and full-subtractor, are proposed by the proposed ASDB gates. The simulation results show high output stability as well as adequate robustness, against various defects obtained by the proposed designs; on average, they have improvements of more than 56% and 62%, against DB omission defects and extra cell deposition defects; respectively. Also, the results of the investigations show that the proposed circuits have been improved by 65%, 21% and 2%, in terms of occupied area, energy and occurrence, respectively; compared to the previous works.
Citation - WoS: 5
Citation - Scopus: 6
An Ultra Efficient 2:1 Multiplexer Using Bar-Shaped Pattern in Atomic Silicon Dangling Bond Technology
(Springer, 2024) Rasmi, Hadi; Mosleh, Mohammad; Navimipour, Nima Jafari; Kheyrandish, Mohammad; Computer Engineering; 05. Faculty of Engineering and Natural Sciences; 01. Kadir Has University
As CMOS technology approaches its physical and technical limits, alternative technologies such as nanotechnology or quantum computing are needed to overcome the challenges of lithography, transistor scaling, interconnects, and miniaturization. This article introduces a novel nanotechnology that uses atomic-scale silicon dangling bonds (ASDB) to create high-performance, low-power, nanoscale logic circuits. DBs are atoms that can form basic logic gates on a silicon surface using a scanning tunneling microscope device. ASDB can also be an alternative to the existing complementary metal oxide semiconductor (CMOS) technology. The article also proposes a new bar-shaped pattern to design gates and logic circuits with ASDB nano tecnolgoy. The bar-shaped pattern improves the reliability of the output, reduces the area and power consumption, and solves the problem of interatomic energy effects of ASDB. The article demonstrates the efficiency of the bar-shaped pattern by implementing two-input gates such as AND, NAND, OR, NOR, XOR, XNOR, and a 2:1 multiplexer with ASDB. The article also uses a powerful tool called SiQAD to simulate and verify the performance of the proposed structures with ASDB. According to the simulation results, the proposed logic gates are more energy efficient, stable, and compact than the previous structures. They consume 35% and 24.34% less energy and have 14.18% more stability, respectively.