A cost- and energy-efficient SRAM design based on a new 5 i-p majority gate in QCA nanotechnology

Abstract

Quantum-dot Cellular Automata (QCA) is a revolutionary paradigm in the Nano-scale VLSI market with the potential to replace the traditional Complementary Metal Oxide Semiconductor system. To demonstrate its usefulness, this article provides a QCA-based innovation structure comprising a 5-input (i-p) Majority Gate, which is one of the basic gates in QCA, and a Static Random Access Memory (SRAM) cell with set and reset functionalities. The suggested design, with nominal clock zones, provides a reliable, compact, efficient, and durable configuration that helps achieve the optimal size and latency while decreasing power consumption. Based on the suggested 5 i-p majority gate, the realized SRAM architecture improves energy dissipation by 33.95 %, cell count by 31.34 %, and area by 33.33 % when compared to the most recent design designs. Both the time and the cost have been decreased by 30 % and 53.95 %, respectively.