An Efficient Architecture of Adder Using Fault-Tolerant Majority Gate Based on Atomic Silicon Nanotechnology

Abstract

It is expected that Complementary Metal Oxide Semiconductor (CMOS) implementation with ever-smaller transistors will soon face significant issues such as device density, power consumption, and performance due to the requirement for challenging fabrication processes. Therefore, a new and promising computation paradigm, nanotechnology, can replace CMOS technology. In addition, a new frontier in computing is opened up by nanotechnology called atomic silicon, which has the same extraordinary behavior as quantum dots. Furthermore, Dangling Bond (DB) quantum dots play a vital role in atomic silicon nanotechnology. On the other hand, atomic silicon circuits are highly prone to defects, so suggested fault-tolerant structures in this technology play important roles. The addition operator holds immense significance in digital signal processing and computer arithmetic operations, making it one of the primary operations in digital circuits. Consequently, full adders have gained popularity and find widespread use in efficiently solving mathematical problems. In the following paper, we will explore the development of an efficient fault-tolerant 3-input majority gate (FT-MV3) using DBs, further enhancing the capabilities of digital circuits. A rule-based approach to the redundant DB achieves a less complex and more robust atomic silicon layout for the MV3. We use the powerful SiQAD tool to simulate all the proposed circuits. In addition, to confirm the efficiency of the proposed gate, all common defects, such as single and double dangling bond omission defects and DB dislocation defects, are examined. The suggested majority gate is 100% and 66.66% tolerant against single and double DB omission defects, respectively. Furthermore, a new full adder design is introduced using the suggested FT-MV3 gate. The results show that the suggested full adder is 44.44% and 35.35% tolerant against single and double DB omission defects. Finally, a fault-tolerant four-bit adder is designed based on the proposed full adder. IEEE