A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

dc.authoridNoorallahzadeh, Mojtaba/0000-0002-0337-6324
dc.authoridMosleh, Mohammad/0000-0002-0991-1623
dc.authoridPal, Jayanta/0000-0002-0719-6080
dc.authoridAhmadpour, Seyed-Sajad/0000-0003-2462-8030
dc.authorwosidNoorallahzadeh, Mojtaba/AGS-2968-2022
dc.contributor.authorNoorallahzadeh, Mojtaba
dc.contributor.authorMosleh, Mohammad
dc.contributor.authorAhmadpour, Seyed-Sajad
dc.contributor.authorPal, Jayanta
dc.contributor.authorSen, Bibhash
dc.date.accessioned2023-10-19T15:13:05Z
dc.date.available2023-10-19T15:13:05Z
dc.date.issued2023
dc.department-temp[Noorallahzadeh, Mojtaba; Mosleh, Mohammad] Islamic Azad Univ, Mat & Energy Res Ctr, Dezful Branch, Dezful, Iran; [Ahmadpour, Seyed-Sajad] Kadir Has Univ, Fac Engn & Nat Sci, Dept Comp Engn, Istanbul, Turkiye; [Pal, Jayanta] Tripura Univ, Dept Informat Technol, Agartala, West Tripura, India; [Sen, Bibhash] Natl Inst Engn & Technol, Dept Comp Sci & Technol, Durgapur, Indiaen_US
dc.description.abstractReversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N-1, N-2, and N-3, which are used to develop a novel effective 2-bit PP reversible Vedic multiplier and 4-bit ripples carry adders (RCAs). Moreover, 2-bit Vedic multiplier and RCA are used to develop the 4-bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state-of-the-art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two-bit and four-bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.en_US
dc.identifier.citation10
dc.identifier.doi10.1002/jnm.3089en_US
dc.identifier.issn0894-3370
dc.identifier.issn1099-1204
dc.identifier.issue5en_US
dc.identifier.scopus2-s2.0-85146985650en_US
dc.identifier.scopusqualityQ2
dc.identifier.urihttps://doi.org/10.1002/jnm.3089
dc.identifier.urihttps://hdl.handle.net/20.500.12469/5602
dc.identifier.volume36en_US
dc.identifier.wosWOS:000918261100001en_US
dc.identifier.wosqualityN/A
dc.khas20231019-WoSen_US
dc.language.isoenen_US
dc.publisherWileyen_US
dc.relation.ispartofInternational Journal of Numerical Modelling-Electronic Networks Devices and Fieldsen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectDot Cellular-AutomataEn_Us
dc.subjectEfficient DesignEn_Us
dc.subjectAlgorithmEn_Us
dc.subjectAdderEn_Us
dc.subjectGatesEn_Us
dc.subjectDot Cellular-Automata
dc.subjectparity preservingen_US
dc.subjectEfficient Design
dc.subjectquantum circuiten_US
dc.subjectAlgorithm
dc.subjectquantum costen_US
dc.subjectAdder
dc.subjectreversible logicen_US
dc.subjectGates
dc.subjectVedic multiplieren_US
dc.titleA new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuitsen_US
dc.typeArticleen_US
dspace.entity.typePublication

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