A new design of a digital filter for an efficient field programmable gate array using quantum dot technology
dc.authorid | Ahmed, Suhaib/0000-0003-3496-8856 | |
dc.authorscopusid | 57216864558 | |
dc.authorscopusid | 57202686649 | |
dc.authorscopusid | 57200178626 | |
dc.authorscopusid | 55897274300 | |
dc.authorscopusid | 56912219900 | |
dc.authorscopusid | 58833344600 | |
dc.authorwosid | Ahmed, Suhaib/AAC-7092-2019 | |
dc.contributor.author | Taghavirashidizadeh, Ali | |
dc.contributor.author | Ahmadpour, Seyed-Sajad | |
dc.contributor.author | Ahmed, Suhaib | |
dc.contributor.author | Navimipour, Nima Jafari | |
dc.contributor.author | Kassa, Sankit Ramkrishna | |
dc.contributor.author | Yalcin, Senay | |
dc.date.accessioned | 2024-06-23T21:37:04Z | |
dc.date.available | 2024-06-23T21:37:04Z | |
dc.date.issued | 2024 | |
dc.department | Kadir Has University | en_US |
dc.department-temp | [Taghavirashidizadeh, Ali] Islamic Azad Univ, Dept Elect & Elect Engn, Cent Tehran Branch IAUCTB, Tehran, Iran; [Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari] Kadir Has Univ, Fac Engn & Nat Sci, Dept Comp Engn, Istanbul, Turkiye; [Ahmed, Suhaib] Chitkara Univ, Inst Engn & Technol, Rajpura, Punjab, India; [Ahmed, Suhaib] Model Inst Engn & Technol, Dept Elect Commun Engn, Jammu, India; [Navimipour, Nima Jafari] Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu 64002, Yunlin, Taiwan; [Kassa, Sankit Ramkrishna] Symbiosis Int Deemed Univ, Symbiosis Inst Technol, Elect & Telecommun Engn Dept, Pune, India; [Yalcin, Senay] Bahcesehir Univ, Sch Engn & Nat Sci, Dept Energy Syst Engn, Istanbul, Turkiye | en_US |
dc.description | Ahmed, Suhaib/0000-0003-3496-8856 | en_US |
dc.description.abstract | Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency. | en_US |
dc.identifier.citation | 0 | |
dc.identifier.doi | 10.1016/j.mseb.2023.117040 | |
dc.identifier.issn | 0921-5107 | |
dc.identifier.issn | 1873-4944 | |
dc.identifier.scopus | 2-s2.0-85179620847 | |
dc.identifier.scopusquality | Q2 | |
dc.identifier.uri | https://doi.org/10.1016/j.mseb.2023.117040 | |
dc.identifier.uri | https://hdl.handle.net/20.500.12469/5690 | |
dc.identifier.volume | 300 | en_US |
dc.identifier.wos | WOS:001139767200001 | |
dc.identifier.wosquality | Q2 | |
dc.language.iso | en | en_US |
dc.publisher | Elsevier | en_US |
dc.relation.publicationcategory | Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı | en_US |
dc.rights | info:eu-repo/semantics/closedAccess | en_US |
dc.subject | Multiply-accumulate (MAC) | en_US |
dc.subject | FPGA | en_US |
dc.subject | Digital Filters | en_US |
dc.subject | Quantum dot cellular automata (QCA) | en_US |
dc.subject | Nano-Design | en_US |
dc.title | A new design of a digital filter for an efficient field programmable gate array using quantum dot technology | en_US |
dc.type | Article | en_US |
dspace.entity.type | Publication |