Fault-tolerant training of neural networks in the presence of MOS transistor mismatches

dc.contributor.authorÖğrenci, Arif Selçuk
dc.contributor.authorDündar, Günhan
dc.contributor.authorBalkır, Sina
dc.date.accessioned2019-06-27T08:01:05Z
dc.date.available2019-06-27T08:01:05Z
dc.date.issued2001
dc.departmentFakülteler, Mühendislik ve Doğa Bilimleri Fakültesi, Elektrik-Elektronik Mühendisliği Bölümüen_US
dc.description.abstractAnalog techniques are desirable for hardware implementation of neural networks due to their numerous advantages such as small size low power and high speed. However these advantages are often offset by the difficulty in the training of analog neural network circuitry. In particular training of the circuitry by software based on hardware models is impaired by statistical variations in the integrated circuit production process resulting in performance degradation. In this paper a new paradigm of noise injection during training for the reduction of this degradation is presented. The variations at the outputs of analog neural network circuitry are modeled based on the transistor-level mismatches occurring between identically designed transistors Those variations are used as additive noise during training to increase the fault tolerance of the trained neural network. The results of this paradigm are confirmed via numerical experiments and physical measurements and are shown to be superior to the case of adding random noise during training.en_US]
dc.identifier.citation10
dc.identifier.doi10.1109/82.924069en_US
dc.identifier.endpage281
dc.identifier.issn1549-7747en_US
dc.identifier.issn1558-3791en_US
dc.identifier.issn1549-7747
dc.identifier.issn1558-3791
dc.identifier.issue3
dc.identifier.scopus2-s2.0-0035268207en_US
dc.identifier.scopusqualityQ1
dc.identifier.startpage272en_US
dc.identifier.urihttps://hdl.handle.net/20.500.12469/245
dc.identifier.urihttps://doi.org/10.1109/82.924069
dc.identifier.volume48en_US
dc.identifier.wosWOS:000168916700005en_US
dc.identifier.wosqualityQ2
dc.institutionauthorÖğrenci, Arif Selçuken_US
dc.language.isoenen_US
dc.publisherIEEE-INST Electrical Electronics Engineers Incen_US
dc.relation.journalIEEE Transactions on Circuits And Systems II-Express Briefsen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectBackpropagationen_US
dc.subjectNeural network hardwareen_US
dc.subjectNeural network trainingen_US
dc.subjectTransistor mismatchen_US
dc.titleFault-tolerant training of neural networks in the presence of MOS transistor mismatchesen_US
dc.typeArticleen_US
dspace.entity.typePublication

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