Browsing by Author "Ahmadpour, Seyed-Sajad"

Now showing 1 - 20 of 33

Citation - WoS: 32
Citation - Scopus: 37
A Cost- and Energy-Efficient Sram Design Based on a New 5 I-P Majority Gate in Qca Nanotechnology
(Elsevier, 2024) Kassa, Sankit; Ahmadpour, Seyed-Sajad; Lamba, Vijay; Misra, Neeraj Kumar; Navimipour, Nima Jafari; Kotecha, Ketan; Jafari Navimipour, Nima; Kumar Misra, Neeraj
Quantum-dot Cellular Automata (QCA) is a revolutionary paradigm in the Nano-scale VLSI market with the potential to replace the traditional Complementary Metal Oxide Semiconductor system. To demonstrate its usefulness, this article provides a QCA-based innovation structure comprising a 5-input (i-p) Majority Gate, which is one of the basic gates in QCA, and a Static Random Access Memory (SRAM) cell with set and reset functionalities. The suggested design, with nominal clock zones, provides a reliable, compact, efficient, and durable configuration that helps achieve the optimal size and latency while decreasing power consumption. Based on the suggested 5 i-p majority gate, the realized SRAM architecture improves energy dissipation by 33.95 %, cell count by 31.34 %, and area by 33.33 % when compared to the most recent design designs. Both the time and the cost have been decreased by 30 % and 53.95 %, respectively.
Citation - WoS: 13
Citation - Scopus: 13
Cost-Effective Synthesis of Qca Logic Circuit Using Genetic Algorithm
(Springer, 2023) Pramanik, Amit Kumar; Mahalat, Mahabub Hasan; Pal, Jayanta; Ahmadpour, Seyed-Sajad; Sen, Bibhash
Quantum-dot cellular automata (QCA) is a field coupling nano-technology that has drawn significant attention for its low power consumption, low area overhead, and achieving a high speed over the CMOS technology. Majority Voter (MV) and QCA Inverter (INV) are the primitive logic in QCA for implementing any QCA circuit. The performance and cost of a QCA circuit directly depend on the number of QCA primitives and their interconnections. Their optimization plays a crucial role in optimizing the QCA logic circuit synthesis. None of the previous works considered elitism in GA, all the optimization objectives (MV, INV and Level), and the redundancy elimination approach. These profound issues lead us to propose a new methodology based on Genetic algorithm (GA) for the cost-effective synthesis of the QCA circuit of the multi-output boolean functions with an arbitrary number of inputs. The proposed method reduces the delay and gate count, where the worst-case delay is minimized in terms of the level. This methodology adapts elitism to preserve the best solutions throughout the intermediate generations. Here, MV, INV, and levels are optimized according to their relative cost factor in a QCA circuit. Moreover, new methodologies are proposed to create the initial population, maintain the variations, and eliminate redundant gates. Simulation results endorse the superiority of the proposed method.
Citation - WoS: 25
Citation - Scopus: 31
Design and Implementation of a Nano-Scale High-Speed Multiplier for Signal Processing Applications
(Elsevier, 2024) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Ul Ain, Noor; Kerestecioglu, Feza; Yalcin, Senay; Avval, Danial Bakhshayeshi; Hosseinzadeh, Mehdi; Ain, Noor Ul
Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technologybased multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.
Citation - WoS: 21
Citation - Scopus: 23
An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform
(Elsevier, 2022) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Das, Jadav Chandra; De, Debashis; Yalcin, Senay
Quantum-dot cellular automata (QCA) is a domain coupling nano-technology that has drawn significant attention for less power consumption, area, and design overhead. It is able to achieve a high speed over the CMOS technology. Recently, the tendency to design reversible circuits has been expanding because of the reduction in energy dissipation. Hence, the QCA is a crucial candidate for reversible circuits in nano-technology. On the other hand, the addition operator is also considered one of the primary operations in digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, full-adders have become popular and extensively solve mathematical problems more efficiently and faster. They are one of the essential fundamental circuits in most digital processing circuits. Therefore, this article first suggests a novel reversible block called the RF-adder block. Then, an effective reversible adder design is proposed using the recommended reversible RF-adder block. The QCAPro and QCADesigner 2.0.3 tools were employed to assess the effectiveness of the suggested reversible full-adder. The outcomes of energy dissipation for the proposed circuit compared to the best previous structure at three different tunneling energy levels indicate a reduction in the power consumption by 45.55%, 38.82%, and 34.62%, respectively. (C) 2022 Elsevier B.V. All rights reserved.
Citation - WoS: 8
Citation - Scopus: 8
An Efficient Architecture of Adder Using Fault-Tolerant Majority Gate Based on Atomic Silicon Nanotechnology
(Ieee-inst Electrical Electronics Engineers inc, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Bahar, Ali Newaz; Yalcin, Senay
It is expected that Complementary Metal Oxide Semiconductor (CMOS) implementation with ever-smaller transistors will soon face significant issues such as device density, power consumption, and performance due to the requirement for challenging fabrication processes. Therefore, a new and promising computation paradigm, nanotechnology, can replace CMOS technology. In addition, a new frontier in computing is opened up by nanotechnology called atomic silicon, which has the same extraordinary behavior as quantum dots. On the other hand, atomic silicon circuits are highly prone to defects, so suggested fault-tolerant structures in this technology play important roles. The full adders have gained popularity and find widespread use in efficiently solving mathematical problems. In the following article, we will explore the development of an efficient fault-tolerant 3-input majority gate (FT-MV3) using DBs, further enhancing the capabilities of digital circuits. A rule-based approach to the redundant DB achieves a less complex and more robust atomic silicon layout for the MV3. We use the SiQAD tool to simulate proposed circuits. In addition, to confirm the efficiency of the proposed gate, all common defects, such as single and double dangling bond omission defects and DB dislocation defects, are examined. The suggested gate is 100% and 66.66% tolerant against single and double DB omission defects, respectively. Furthermore, a new adder design is introduced using the suggested FT-MV3 gate. The results show that the suggested adder is 44.44% and 35.35% tolerant against single and double DB omission defects. Finally, a fault-tolerant four-bit adder is designed based on the proposed adder.
Citation - WoS: 36
Citation - Scopus: 42
An Efficient Design of Multiplier for Using in Nano-Scale Iot Systems Using Atomic Silicon
(IEEE-Inst Electrical Electronics Engineers Inc, 2023) Ahmadpour, Seyed-Sajad; Heidari, Arash; Navimpour, Nima Jafari; Asadi, Mohammad-Ali; Yalcin, Senay
Because of recent technological developments, such as Internet of Things (IoT) devices, power consumption has become a major issue. Atomic silicon quantum dot (ASiQD) is one of the most impressive technologies for developing low-power processing circuits, which are critical for efficient transmission and power management in micro IoT devices. On the other hand, multipliers are essential computational circuits used in a wide range of digital circuits. Therefore, the multiplier design with a low occupied area and low energy consumption is the most critical expected goal in designing any micro IoT circuits. This article introduces a low-power atomic silicon-based multiplier circuit for effective power management in the micro IoT. Based on this design, a $4\times 4$ -bit multiplier array with low power consumption and size is presented. The suggested circuit is also designed and validated using the SiQAD simulation tool. The proposed ASiQD-based circuit significantly reduces energy consumption and area consumed in the micro IoT compared to most recent designs.
Citation - WoS: 18
Citation - Scopus: 19
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm
(IEEE-Inst Electrical Electronics Engineers Inc, 2023) Ahmadpour, Seyed-Sajad; Jafari Navimipour, Nima; Bahar, Ali Nawaz; Mosleh, Mohammad; Yalcin, Senay
Area overhead and energy consumption continue to dominate the scalability issues of modern digital circuits. In this context, atomic silicon and reversible logic have emerged as suitable alternatives to address both issues. In this article, the authors propose novel nano-scale circuit design with low area and energy overheads using the same. In particular, the authors propose a reversible gate with Miller algorithm and atomic silicon technology. This article is extremely relevant in todays era, when the world is moving toward low area and low energy circuits for use in edge devices.
Energy-Efficient Code Conversion Using Quantum-Dot Nano-Architectures for Internet of Things (IoT) Applications
(Springer, 2026) Chugh, Hemanshi; Patidar, Mukesh; Ahmadpour, Seyed-Sajad; Zohaib, Muhammad
Internet of Things (IoT) is a developing technological trend in which common real-world objects are connected with technologies of sensors, actuators, and communication units, allowing data collection, sharing, and processing via the Internet. One of the important circuits in IoT systems is code converter circuits, which are critical components in data formatting, arithmetic processing, and error-resistant processing in these systems, and hence, have a direct influence on performance and energy resources. However, complementary metal-oxide-semiconductor-based realizations of these converters suffer important drawbacks, including high occupied area, increased power dissipation, propagation delays, and longer latency, and are not suitable in ultra-compact and energy-constrained IoT devices. To overcome these challenges, emerging technologies like the quantum-dot cellular automata (QCA) are offering new alternatives, featuring ultra-low power consumption, low area, and high processing speed, which would make QCA technologies suitable for next-generation IoT applications. This paper proposes high-density and power-efficient bidirectional code converter circuits (BCD to Excess-3-B2X3C and Excess-3 to BCD-X3B2C converters) utilizing QCA technology. In addition, significant improvements are demonstrated by the comparative evaluations, which include an improvement of 7.89% in cells, a reduction of 25% in area-delay cost (A x D2), and a 43.75% in figure of merit (FoM), respectively. Additionally, QCADesigner and QCAPro simulation and power analysis indicate that the switching energy is generally low throughout a wide variety of tunneling energies. The presented QCA-based single layer is more scalable than current designs, which makes it suitable for future IoT integration.
Citation - WoS: 1
High-Performance and Low-Power Quantum-Dot Multiply-Accumulate Design for Next-Generation Supercomputing Platforms
(Springer, 2026) Ahmadpour, Seyed-Sajad; Zohaib, Muhammad; Rasmi, Hadi; Jafari Navimipour, Nima
The rapid growth of high-performance computing (HPC) and supercomputing applications necessitates hardware architectures that provide both high computational performance and strong energy efficiency under real-time and massively parallel workloads. However, conventional complementary metal-oxide semiconductor (CMOS) technologies face fundamental challenges, including excessive power consumption, leakage currents, and severe scaling limitations, which restrict their suitability for future exascale systems. To overcome these limitations, emerging nanotechnologies such as Quantum-dot Cellular Automata (QCA) have gained significant attention due to their ultra low-power consumption and high device density. In this work, we present a high-performance and low-power Quantum-Dot Multiply-Accumulate (Q-Dot MAC) unit, where MAC denotes a fundamental arithmetic operation combining multiplication and accumulation, extensively used in scientific computing, and signal processing. The proposed QCA-based architecture is specifically designed to satisfy the high-frequency (HF) operational demands of modern HPC environments, enabling sustained high-throughput computation. The main objective of this design is to realize a compact, energy-efficient, and physically stable MAC unit suitable for large-scale deployment in energy-constrained supercomputing platforms. Exploiting the inherent parallelism and high-density layout characteristics of QCA, the proposed MAC architecture efficiently executes key computational kernels required in HPC workloads, including large-scale matrix multiplication, convolution operations, and scientific simulations. The proposed QCA-based circuits demonstrate significant performance and area efficiency improvements compared with the best existing designs in the literature. Specifically, the half adder (HA) achieves a 20.51% reduction in cell count and a 25% reduction in area, and the complete MAC unit provides a 22.84% decrease in cell count, a 9.03% reduction in occupied area and a 14.25% in delay. These results confirm the efficiency and scalability of the proposed design. The low-area enables the integration of large arrays of MAC units, facilitating scalable systolic and Single Instruction Multiple Data (SIMD) architectures required in supercomputing environments.
High-Performance and Low-Power Quantum-Dot-Based Multiply-Accumulate Design for next-Generation Supercomputing Platforms (Vol 82, 207, 2026)
(Springer, 2026) Navimipour, Nima Jafari; Ahmadpour, Seyed-Sajad; Rasmi, Hadi; Zohaib, Muhammad
Citation - WoS: 6
Citation - Scopus: 8
High-Speed and Area-Efficient Arithmetic and Logic Unit Architecture Using Quantum-Dot Cellular Automata for Digital Signal Processing
(Elsevier, 2025) Zohaib, Muhammad; Navimipour, Nima Jafari; Aydemir, Mehmet Timur; Ahmadpour, Seyed-Sajad
Signal processing has significantly influenced our lives in many domains, including telecommunications, education, healthcare, industry, and security. The efficiency of signal processing heavily relies on the Arithmetic and Logic Unit (ALU), which stands as an essential hardware component. In addition, ALU is a fundamental part of a central processing unit (CPU), leading to fundamental operations inside the processor. However, the growing demand for small, robust hardware systems has led researchers to create nano-electronic technologies under consideration. One of the leading technologies in this field is Quantum-dot cellular automata (QCA), which demonstrates promising value as a possible alternative to complementary metal-oxide-semiconductor (CMOS) designs since it enables compact circuit designs with minimal power consumption. The existing QCA-based ALU designs face limitations in cell count density together with high occupied area and high delay, which reduces their performance for real-time signal processing. This research presents a 1-bit ALU through a QCA-optimized approach for DSP applications. QCADesigner is used to validate and verify all proposed designs. Results show a statistically significant improvement in cell count reduction of 46.84 % and a total occupied area of 64.28 % lower than the most advanced version published to date.
A Low-Latency and Area-Efficient QCA-Based Quantum-Dot Design for Next-Generation Digital Sustainable Systems
(Elsevier, 2025) Zohaib, Muhammad; Ahmadpour, Seyed-Sajad; Rasmi, Hadi; Khan, Angshuman; Navimipour, Nima Jafari
Digital sustainable system plays a vital role in the advancement of dynamic industries, including agriculture, healthcare, smart cities, Edge Artificial Intelligence (AI), and the Internet of Things (IoT), by facilitating highspeed, low-power, and highly compressed processing. These systems are based on the capabilities of real-time execution, processing, and analysis of large-scale information with extreme power and area limitations. However, traditional Arithmetic Logic Units (ALUs) based on complementary metal-oxide semiconductors (CMOS) are becoming challenging in terms of scalability, power consumption, space demand, and nanoscale fabrication. The ALU is one of the most important parts of such systems and has a direct effect on the overall computing performance, but current implementations cannot sustain the requirements of next-generation applications. To overcome these shortcomings, this paper offers an area-efficient and low-latency ALU that can be designed with the quantum-dot cellular automata (QCA) technology, with the advantage of employing area-efficient layout and simple cell design. The proposed QCA-based ALU has high performance, less delay, and less energy consumption, which makes it properly suitable for the next generation of digital sustainable systems applications. The outcome of the simulation indicates that there are considerable performance gains, such as an 82.37% decrease in energy consumption, and a 9.21% decrease in area relative to current available design. These enhancements emphasize the power of QCA technology as a scalable and low-energy consumption alternative to CMOS in the realization of critical computing components in sustainable digital systems.
Citation - WoS: 1
Citation - Scopus: 1
A Nano-Design of Image Masking and Steganography Structure Based on Quantum Technology
(Elsevier, 2025) Salahov, Huseyn; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Das, Jadav Chandra; Rasmi, Hadi
Secure image storage and transmission require sound encryption methods that resist key exposure while maintaining high image quality. Various encryption approaches have been developed to protect image content and its transmission from unauthorized access. One such method is image masking, where a special mask is generated to conceal information within the original image. Instead of hiding the image visually, the mask creates an intermediate layer that obfuscates the encryption key, eliminating the need to transmit it directly. However, implementing such masking techniques efficiently at the hardware level poses particular challenges. Traditional Complementary Metal-Oxide-Semiconductor (CMOS)-based Very-Large-Scale-Integration (VLSI) systems face scalability issues, excessive heat, and high-power consumption. To overcome these challenges, this study utilizes a nano-scale image masking architecture based on Quantum-dot Cellular Automata (QCA), offering reduced area, lower power dissipation, and faster processing. The core operations utilize a three-input XOR gate, designed as a single-layer QCA structure without rotated cells. While QCA-based approaches improve hardware efficiency, most existing implementations focus only on grayscale images, leaving a gap in colorful image encryption. To address this, the work presents a QCA-based encryption and masking architecture for colored images. The method encrypts an image using a random key to generate a cipher image, which is then XORed with the original image to produce a mask. This process, applied independently to each RGB channel, produces three cipher-mask pairs, embedding steganographic property by concealing key information within the image. The keys are generated using a true random number generator (TRNG) based on cross-coupled loops and crossoriented structures, ensuring high entropy. The design was modeled in QCADesigner 2.0.3, with the encryption/decryption algorithms implemented in Python. Experimental results demonstrated a meaningful reduction in cell count and consumed area compared to the prior designs. Image quality and security analysis confirmed visual fidelity and improved robustness.
Citation - WoS: 32
Citation - Scopus: 34
A Nano-Scale Arithmetic and Logic Unit Using a Reversible Logic and Quantum-Dots
(Springer, 2023) Navimipour, Nima Jafari; Ahmadpour, Seyed-Sajad; Yalcin, Senay
The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs.
Citation - WoS: 19
Citation - Scopus: 20
A Nano-Scale Design of Arithmetic and Logic Unit for Energy-Efficient Signal Processing Devices Based on a Quantum-Based Technology
(Springer, 2025) Zohaib, Muhammad; Navimipour, Nima Jafari; Aydemir, Mehmet Timur; Ahmadpour, Seyed-Sajad
Signal processing had a significant impact on the development of many elements of modern life, including telecommunications, education, healthcare, industry, and security. The semiconductor industry is the primary driver of signal processing innovation, producing ever-more sophisticated electronic devices and circuits in response to global demand. In addition, the central processing unit (CPU) is described as the "brain" of a computer or all electronic devices and signal processing. CPU is a critical electronic device that includes vital components such as memory, multiplier, adder, etc. Also, one of the essential components of the CPU is the arithmetic and logic unit (ALU), which executes the arithmetic and logical operations within all types of CPU operations, such as addition, multiplication, and subtraction. However, delay, occupied areas, and energy consumption are essential parameters in ALU circuits. Since the recent ALU designs experienced problems like high delay, high occupied area, and high energy consumption, implementing electronic circuits based on new technology can significantly boost the performance of entire signal processing devices, including microcontrollers, microprocessors, and printed devices, with high-speed and low occupied space. Quantum dot cellular automata (QCA) is an effective technology for implementing all electronic circuits and signal processing applications to solve these shortcomings. It is a transistor-less nanotechnology being explored as a successor to established technologies like CMOS and VLSI due to its ultra-low power dissipation, high device density, fast operating speed in THz, and reduced circuit complexity. This research proposes a ground-breaking ALU that upgrades electrical devices such as microcontrollers by applying cutting-edge QCA nanotechnology. The primary goal is to offer a novel ALU architecture that fully utilizes the potential of QCA nanotechnology. Using a new and efficient approach, the fundamental gates are skillfully utilized with a coplanar layout based on a single cell not rotated. Furthermore, this work presents an enhanced 1-bit and 2-bit arithmetic logic unit in quantum dot cellular automata. The recommended design includes logic, arithmetic operations, full adder (FA) design, and multiplexers. Using the powerful simulation tools QCADesigner, all proposed designs are evaluated and verified. The simulation outcomes indicates that the suggested ALU has 42.48 and 64.28% improvements concerning cell count and total occupied area in comparison to the best earlier single-layer and multi-layer designs.
Citation - WoS: 11
Citation - Scopus: 13
A Nano-Scale Design of Vedic Multiplier for Electrocardiogram Signal Processing Based on a Quantum Technology
(Aip Publishing, 2025) Wang, Yuyao; Darbandi, Mehdi; Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Navin, Ahmad Habibizad; Heidari, Arash; Anbar, Mohammad
An electrocardiogram (ECG) measures the electric signals from the heartbeat to diagnose various heart issues; nevertheless, it is susceptible to noise. ECG signal noise must be removed because it significantly affects ECG signal characteristics. In addition, speed and occupied area play a fundamental role in ECG structures. The Vedic multiplier is an essential part of signal processing and is necessary for various applications, such as ECG, clusters, and finite impulse response filter architectures. All ECGs have a Vedic multiplier circuit unit that is necessary for signal processing. The Vedic multiplier circuit always performs multiplication and accumulation steps to execute continuous and complex operations in signal processing programs. Conversely, in the Vedic multiplier framework, the circuit speed and occupied area are the main limitations. Fixing these significant defects can drastically improve the performance of this crucial circuit. The use of quantum technologies is one of the most popular solutions to overcome all previous shortcomings, such as the high occupied area and speed. In other words, a unique quantum technology like quantum dot cellular automata (QCA) can easily overcome all previous shortcomings. Thus, based on quantum technology, this paper proposes a multiplier for ECG using carry skip adder, half-adder, and XOR circuits. All suggested frameworks utilized a single-layer design without rotated cells to increase their operability in complex architectures. All designs have been proposed with a coplanar configuration in view, having an impact on the circuits' durability and stability. All proposed architectures have been designed and validated with the tool QCADesigner 2.0.3. All designed circuits showed a simple structure with minimum quantum cells, minimum area, and minimum delay with respect to state-of-the-art structures.
Citation - WoS: 43
Citation - Scopus: 53
A Nano-Scale N-Bit Ripple Carry Adder Using an Optimized Xor Gate and Quantum-Dots Technology With Diminished Cells and Power Dissipation
(Elsevier, 2023) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Mosleh, Mohammad; Bahar, Ali Newaz; Yalcin, Senay
In the nano-scale era, quantum-dot cellular automata (QCA) technology has become an appealing substitute for transistor-based technologies. QCA will be the preferred technology for developing the next generation of digital systems. On the other hand, the full-adder and ripple carry adder (RCA) are the crucial building blocks of complex circuits, the most used structures in digital operations systems, and a practical part of the most well-known complex circuits in QCA technology. In addition, this technology was used to design the full adder for several procedures, like multiplication, subtraction, and division. For this reason, the full adder is generally investigated as a central unit and microprocessor in developing QCA technology. Furthermore, most previous QCA-based adder structures have suffered from some drawbacks, such as a high number of cells, high energy consumption, the high number of gates, and the placement of inputs and outputs in a closed loop; hence, the implementation of an efficient adder with only one gate and a low number of cells, such as exclusive-OR (XOR) gate, can solve all previous problems. Therefore, in this paper, a significantly improved structure of 3-input XOR is suggested based on the promising QCA technology. In addition, a QCA clocking mechanism and explicit cell interaction form the foundation of the proposed QCA-based XOR gate configuration. This gate can be easily converted into an adder circuit while containing a small number of cells and being extremely compressed. The suggested QCA-based XOR design is focused on optimizing a single-bit adder using cellular interaction. The suggested single-bit adder contains 14 cells. Based on this adder, several different RCAs, such as 4, 8, 16, and 32-bit, are designed. The comparison of the proposed single-bit adder to the best coplanar and multi-layer ones shows a 51.72% and 36.36% reduction of cells, respectively. In addition, all suggested designs are verified through simulation using QCADesigner and QCAPro. Finally, many physical validations are provided to approve the functionality of the suggested XOR design.(c) 2023 Elsevier B.V. All rights reserved.
Citation - Scopus: 1
A Nano-Scale Quantum-Dot Multiplexer Architecture for Logic Units in Internet of Things Healthcare Systems
(Elsevier, 2025) Safoev, Nuriddin; Karimov, Madjit; Ahmadpour, Seyed-Sajad; Zohaib, Muhammad; Tashev, Komil; Ahmed, Suhaib
The Internet of Things (IoT) is a propelling technological shift that enables seamless networking between billions of physical devices across healthcare sectors, agriculture, smart cities, and industrial production lines. By integrating embedded sensors, actuators, and communication modules, IoT systems can gather real-time data, leading to better operational decisions and improved efficiency in healthcare systems. The rapid growth of IoT devices creates three main operational challenges related to power usage, efficiency, and thermal management requirements. The demand for more efficient, compact, high-speed, and energy-efficient devices poses significant challenges for these systems. Traditional complementary metal-oxide-semiconductor (CMOS)-based architectures struggle to meet these demanding requirements, representing a major barrier to the development of reliable and scalable next-generation IoT systems. This research demonstrates Quantum-Dot Cellular Automata (QCA) nanotechnology as an alternative solution because it performs logical operations through electron positioning rather than conventional current flow. This paper proposes a modified version of a QCA-based multiplexer design (MUX) since digital logic systems require these signal routing elements for operation. The fundamental 2:1 MUX is established using QCA cell-interaction principles, and then 4:1 and 8:1 QCA MUXs are designed through hierarchical expansion. The suggested modified MUX devices operate on a compact scale with minimal cells to reduce the occupied area compared to current MUX designs. The research outcomes demonstrate that QCA circuits hold promising potential for creating energy-saving, powerful, and scalable computational platforms for future IoT healthcare systems.
Citation - WoS: 14
Citation - Scopus: 17
A New Design of a Digital Filter for an Efficient Field Programmable Gate Array Using Quantum Dot Technology
(Elsevier, 2024) Taghavirashidizadeh, Ali; Ahmadpour, Seyed-Sajad; Ahmed, Suhaib; Navimipour, Nima Jafari; Kassa, Sankit Ramkrishna; Yalcin, Senay; Jafari Navimipour, Nima; Ramkrishna Kassa, Sankit
Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.
Citation - WoS: 30
Citation - Scopus: 37
A New Design of Parity Preserving Reversible Vedic Multiplier Targeting Emerging Quantum Circuits
(Wiley, 2023) Noorallahzadeh, Mojtaba; Mosleh, Mohammad; Ahmadpour, Seyed-Sajad; Pal, Jayanta; Sen, Bibhash
Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N-1, N-2, and N-3, which are used to develop a novel effective 2-bit PP reversible Vedic multiplier and 4-bit ripples carry adders (RCAs). Moreover, 2-bit Vedic multiplier and RCA are used to develop the 4-bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state-of-the-art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two-bit and four-bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.