Browsing by Author "Kassa, Sankit"

Now showing 1 - 3 of 3

Citation Count: 0
A cost- and energy-efficient SRAM design based on a new 5 i-p majority gate in QCA nanotechnology
(Elsevier, 2024) Kassa, Sankit; Ahmadpour, Seyed-Sajad; Lamba, Vijay; Misra, Neeraj Kumar; Navimipour, Nima Jafari; Kotecha, Ketan
Quantum-dot Cellular Automata (QCA) is a revolutionary paradigm in the Nano-scale VLSI market with the potential to replace the traditional Complementary Metal Oxide Semiconductor system. To demonstrate its usefulness, this article provides a QCA-based innovation structure comprising a 5-input (i-p) Majority Gate, which is one of the basic gates in QCA, and a Static Random Access Memory (SRAM) cell with set and reset functionalities. The suggested design, with nominal clock zones, provides a reliable, compact, efficient, and durable configuration that helps achieve the optimal size and latency while decreasing power consumption. Based on the suggested 5 i-p majority gate, the realized SRAM architecture improves energy dissipation by 33.95 %, cell count by 31.34 %, and area by 33.33 % when compared to the most recent design designs. Both the time and the cost have been decreased by 30 % and 53.95 %, respectively.
Citation Count: 1
A novel design of coplanar 8-bit ripple carry adder using field-coupled quantum-dot cellular automata nanotechnology
(Springer Heidelberg, 2023) Kassa, Sankit; Misra, Neeraj Kumar; Ahmadpour, Seyed Sajad; Lamba, Vijay; Vadthiya, Narendar
Quantum-dot cellular automata (QCA) is a prominent research field that can replace MOS technology due to constraints of short-channel effects, power consumption and lithography costs. This manuscript presents novel and efficient designs of various combinational circuits that are XOR gate, half adders (HA), full adders (FA), half subtractor (HS), full subtractor (FS), ripple carry adder (RCA) and (2 x 1) multiplexer. This study presents an innovative concept for digital circuits that can be implemented in a single layer by using 90 & DEG; cells in clock zones. The suggested circuit architectures are relatively basic and straightforward to construct a robust QCA layout. One may reduce the overall size and the number of QCA cells by using the aforementioned designs and incorporating them into bigger circuits, such as the 4-bit and 8-bit RCA. Every design suggested in the study is compared to a design already published in the literature, and it is discovered that the suggested designs are much superior in terms of latency, area, number of cells and gate counts. QCADesigner tool confirms the functional correctness of proposed circuits. All newly created FAs, Design 1, Design 2, Design 3 and Design 4, exhibit cell count improvements of 18.88%, 40%, 46.66% and 4.44%, respectively, compared to the best-reported design. The area efficiency improves by up to 83.6% and 35.11%, respectively, while the cell count improves by 67.8% and 25.15% for 4-bit and 8-bit RCA adders, indicating that they are more suited for computational sciences.
Citation Count: 2
An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots
(Pergamon-Elsevier Science Ltd, 2023) Ahmadpour, Seyed-Sajad; Navimipour, Nima Jafari; Kassa, Sankit; Misra, Neeraj Kumar; Yalcin, Senay
Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.