An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots

dc.authoridMisra, Neeraj Kumar/0000-0002-7907-0276
dc.authorwosidMisra, Neeraj Kumar/B-9442-2015
dc.contributor.authorJafari Navimipour, Nima
dc.contributor.authorNavimipour, Nima Jafari
dc.contributor.authorKassa, Sankit
dc.contributor.authorMisra, Neeraj Kumar
dc.contributor.authorYalcin, Senay
dc.date.accessioned2023-10-19T15:12:13Z
dc.date.available2023-10-19T15:12:13Z
dc.date.issued2023
dc.department-temp[Ahmadpour, Seyed-Sajad] Kadir Has Univ, Fac Engn & Nat Sci, Dept Comp Engn, Istanbul, Turkiye; [Navimipour, Nima Jafari] Natl Yunlin Univ Sci & Technol, Future Technol Res Ctr, Touliu 64002, Taiwan; [Kassa, Sankit] Symbiosis Int Deemed Univ, Symbiosis Inst Technol, Elect & Telecommun Engn Dept, Pune, India; [Misra, Neeraj Kumar] VIT AP Univ, Sch Elect Engn, Amaravathi 522237, Andhra Pradesh, India; [Yalcin, Senay] Nisantasi Univ, Dept Comp Engn, Istanbul, Turkiyeen_US
dc.description.abstractQuantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.en_US
dc.description.sponsorshipMinistry of Science and Technology (MOST) , Taiwan [MOST 110-2222-E-224- 002-MY3]en_US
dc.description.sponsorshipThis work was supported in part by the Ministry of Science and Technology (MOST) , Taiwan, under Grant MOST 110-2222-E-224- 002-MY3.en_US
dc.identifier.citation2
dc.identifier.doi10.1016/j.compeleceng.2023.108865en_US
dc.identifier.issn0045-7906
dc.identifier.issn1879-0755
dc.identifier.scopus2-s2.0-85166229431en_US
dc.identifier.scopusqualityQ1
dc.identifier.urihttps://doi.org/10.1016/j.compeleceng.2023.108865
dc.identifier.urihttps://hdl.handle.net/20.500.12469/5379
dc.identifier.volume110en_US
dc.identifier.wosWOS:001048789300001en_US
dc.identifier.wosqualityQ2
dc.khas20231019-WoSen_US
dc.language.isoenen_US
dc.publisherPergamon-Elsevier Science Ltden_US
dc.relation.ispartofComputers & Electrical Engineeringen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectFull-AdderEn_Us
dc.subjectFull-Adderen_US
dc.subjectCellular-AutomataEn_Us
dc.subjectDecoderen_US
dc.subjectError Probability Modelen_US
dc.subjectFull-Adder
dc.subjectFault-tolerant 3-input majority gate (FTMG)en_US
dc.subjectCellular-Automata
dc.subjectPower Consumptionen_US
dc.titleAn ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dotsen_US
dc.typeArticleen_US
dspace.entity.typePublication
relation.isAuthorOfPublication0fb3c7a0-c005-4e5f-a9ae-bb163df2df8e
relation.isAuthorOfPublication.latestForDiscovery0fb3c7a0-c005-4e5f-a9ae-bb163df2df8e

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